The present invention relates to a semiconductor memory, and in particular, to a synchronous semiconductor memory having a signal input circuit.
A signal input system of a typical synchronous semiconductor memory such as a synchronous dynamic random access memory (DRAM) is shown in Japanese Laid-Open Patent Application No. 8-180677 (hereinafter, referred to as conventional example 1). In such a system, an internal clock signal is generated based upon a reference clock signal, which is input from the outside, and a clock enable signal for enabling or disabling the reference clock signal. All operations of the other synchronizing circuits in the semiconductor memory are synchronized with the internal clock signal and associated clock signals which are generated from the internal clock signal.
The process of receiving a command signal from the outside and generating an internal command signal that determines the internal operation is shown, for example, in Japanese Laid-Open Patent Application No. 8-17182 (hereinafter, referred to as conventional example 2).
FIG. 1 is a block diagram of a semiconductor circuit, used with a semiconductor memory shown in the conventional examples 1 and 2. FIG. 2 is a timing chart showing operation of the semiconductor circuit of FIG. 1. The semiconductor circuit of FIG. 1 is generally called a timing generator (TG).
In FIGS. 1 and 2, signals CLK, CKE, CSB, RASB, CASB and WEB are input from the outside. The signal CLK is an external reference clock signal, and all the operations of the internal circuits are synchronized with the leading edge of the signal CLK. The signal CKE is an external clock enable signal. When the level of the signal CKE is a logic low (or "non-active" state), no internal operation is performed for the next cycle following the rising edge of the signal CLK. The signals CSB, RASB, CASB and WEB are external command signals, namely, a chip select signal, a row address strobe signal, a column address strobe signal and a write enable signal, respectively. Internal operation of the memory is determined by a combination of signal levels of these signals when the signal CLK rises.
Receiver circuits 11-16 act as input buffers to convert voltage levels of each external input signal, such as the levels of low-voltage transistor-transistor logic (LVTTL), into corresponding internal signal voltage levels. Since each receiver circuit converts only the level, there is no logical difference between the input and the output.
An internal clock generating circuit 1 generates an internal reference clock signal ICLK based on the signal CLK and the signal CKE. The signal ICLK contains logical components of the signal CLK and the signal CKE, and the other internal circuits are operated synchronously with the internal clock signal ICLK.
Latch circuits 21-24 execute latching processing of respective external command signals based on the signal ICLK to control setup time and hold time of the external command signals with respect to the signal CLK. Delay circuits 53-56 regulate the setup time and the hold time. Since it takes much time for the internal clock generating circuit 1 to generate the signal ICLK from the signal CLK and the signal CKE and distribute it to each latch circuit 21-24, the delay circuits 53-56 cause a delay which corresponds to the delay time of circuit 1.
Command decoders 31.sub.0 through 31.sub.n (n is a natural number) activate one of a plurality of respective internal command signals S71.sub.0 through S71.sub.n (or inactivate all of them) which are latched as the combination of signals S81.sub.0 through S81.sub.n output from respective latch circuits 41.sub.0 through 41.sub.n.
Since signals S61-S64 are input to the command decoders 31.sub.0 through 3l.sub.n through different paths, respective outputs of the command decoders 31.sub.0 through 31.sub.n contain a hazard that may cause malfunction of the internal circuits to which the hazard is input. For this reason, the hazard is eliminated by means of the latch circuits 41.sub.0 through 41.sub.n.
The latch circuits 41.sub.0 through 41.sub.n are driven by an internal clock delay signal (ICLKD). Since it takes some delay time for the command decoders 31.sub.0 through 31.sub.n to generate the respective signals S71.sub.0 through S71.sub.n from the signals S61-S64, the signal ICLKD is generated from the signal ICLK through a delay circuit 51 which provides a delay corresponding to the delay time of the command decoders 31.sub.0 through 31.sub.n.
The output signals S81.sub.0 through S81.sub.n of the latch circuits 41.sub.0 through 41.sub.n are internal command signals by which the internal operation of the synchronous DRAM is started.
The critical path for generation of the internal command signals S81.sub.0 through S81.sub.n is as follows: The critical path starts from the CLK input, and passes through the receivers 11 and 12, the internal clock generating circuit 1, the latch circuits 21-24 and the command decoders 31.sub.0 through 31.sub.n, in that order, to reach the latch circuits 41.sub.0 through 41.sub.n from which the internal command signals S81.sub.0 through S81.sub.n are output.
However, such a conventional semiconductor circuit can not latch the external command signals until the internal clock signal ICLK is generated. For this reason, all the operations to be performed after command decoding are affected by the time lag of the internal clock generating circuit 1, and as a result, the access speed of the memory is low.